As it is well known, the widespread use of multimedia applications and the expansion of these applications require a management of a greater and greater amount of data to be stored on a smaller and smaller space to favor a further miniaturization of memory devices provided with multimedia applications.
A first known solution to meet this need is that of storing at least two bits per memory cell thus realizing a non volatile memory device of the multilevel type which, instead of storing only one bit per cell, substantially allows doubling the device capacity for storing information with the circuit area occupied being the same.
The reading of multilevel devices occurs per page, i.e. plural memory words are read in parallel.
To maintain the standards of reliability within multilevel memories, the possibility is provided of an automatic correction of one or more bits by means of suitable parity bits added to the packet of words read in parallel. The definition of a correction code implies the impossibility of carrying out what is called bit manipulation i.e. the possibility of transforming, during successive programming, all the bits of value ‘1’ into bits of value ‘0’, such an operation traditionally being allowed by the specifications of the flash memories. In fact, each pattern modification implies the modification of the parity code necessary for the correction of the errors and the new calculated value can be incompatible with this impossibility to erase the cells.
Another drawback which equally prevents successive programming of the cell with two bits per cell is the so called floating gate coupling which causes a widening of the distributions of the read thresholds incompatible with the margins provided for the good operation of a multilevel device. This is due to the fact that capacitive couplings are formed between memory cells being topologically near, and this modifies the reading thresholds.
A possible solution to this problem provides the definition of memory regions within the array being programmable only once so as to avoid these intolerable couplings caused by the repeated programming.
However, to have a repeatedly programmable memory, inside the same multilevel device, a programmable region with a bit per cell for storing small amounts of data can be defined. In this way, the memory region is used with half efficiency but allows a more frequent refresh.
This solution, however, is not exempt from drawbacks. In particular, the programming step of a two-level region risks being very burdensome for the application since a preliminary reading of the region of interest for programming must be requested for establishing if the programming is being carried out on virgin cells or not, so as to avoid an undesirable “bit manipulation”. Otherwise, the microprocessor is obliged to manage and dynamically update a map of the state of use of the array.